公开(公告)号：US20230153616A1

公开(公告)日：2023-05-18

申请号：US18148057

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Liron Ain-Kedem ,  Guy Berger ,  Maya Rotbart ,  Guy Zvi Ben Artzi

IPC: G06N3/08 ,  G06F7/523

CPC classification number: G06N3/08 ,  G06F7/523

Abstract: Systems, apparatuses and methods may provide for technology that chains a plurality of convolution operations together, wherein the plurality of convolution operations include one or more one-dimensional (1D) convolution operations and one or more two-dimensional (2D) convolution operations, streams the plurality of convolution operations to shared multiply-accumulate (MAC) hardware, wherein to stream the plurality of convolution operations to the shared MAC hardware, the technology swaps weight inputs to the shared MAC hardware with activation inputs to the shared MAC hardware based on convolution type, and stores output data associated with the plurality of convolution operations to a local memory. Each of the 2D convolution operations may include a multi-cycle multiplication operation.

公开(公告)号：US20220222771A1

公开(公告)日：2022-07-14

申请号：US17709988

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Guy Berger ,  Itai Ostashinsky ,  Rakefet Kol

IPC: G06T1/60 ,  G06T11/40 ,  G06T11/60

Abstract: A device, method, system, or article has multi-directional rolling cache to store image data.