公开(公告)号：US20200243376A1

公开(公告)日：2020-07-30

申请号：US16260632

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Harish GANAPATHY ,  Leonard C. PIPES

IPC: H01L21/762 ,  H01L27/108

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.