公开(公告)号：US20220406352A1

公开(公告)日：2022-12-22

申请号：US17763172

申请日：2019-12-12

Applicant: Intel Corporation

Inventor： Liu LIU ,  Chuan SUN ,  Hong MA

IPC: G11C8/14 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.