公开(公告)号：US20190146792A1

公开(公告)日：2019-05-16

申请号：US16249870

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  IGOR ERMOLAEV

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to element sorting of vectors are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction; and an execution unit to execute the decoded instruction to: provide storage for a comparison matrix to store a comparison value for each element of an input vector compared against the other elements of the input vector, perform a comparison operation on elements of the input vector corresponding to storage of comparison values above a main diagonal of the comparison matrix, perform a different operation on elements of the input vector corresponding to storage of comparison values below the main diagonal of the comparison matrix, and store results of the comparison operation and the different operation in the comparison matrix.

公开(公告)号：US20160011870A1

公开(公告)日：2016-01-14

申请号：US14327534

申请日：2014-07-09

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  IGOR ERMOLAEV

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30032

Abstract: A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an instruction. The instruction format of the instruction specifies a first input vector, a second input vector and a third input operand. The instruction execution pipeline comprises an instruction decode stage to decode the instruction. The instruction execution pipeline includes a functional unit to execute the instruction. The functional unit includes a routing network to route a first contiguous group of elements from a first end of one of the input vectors to a second end of the instruction's resultant vector, and, route a second contiguous group of elements from a second end of the other of the input vectors to a first end of the instruction's resultant vector. The first and second ends are opposite vector ends. The first and second groups of contiguous elements are defined from the third input operand. The instruction is not capable of routing non-contiguous groups of elements from the input vectors to the instruction's resultant vector. A software pipeline that uses the instruction is also described

Abstract translation: 描述了具有指令执行流水线的处理器。 指令执行流水线包括取指令的指令提取阶段。 指令的指令格式指定第一输入向量，第二输入向量和第三输入操作数。 指令执行流水线包括用于解码指令的指令解码级。 指令执行流水线包括执行指令的功能单元。 所述功能单元包括路由网络，用于将第一连续的元素组从所述输入向量之一的第一端路由到所述指令的合成向量的第二端，并且从所述第二连续的元素组的第二端 输入向量的其他输入到指令的合成向量的第一端。 第一和第二端是相反的矢量端。 从第三个输入操作数定义第一组和第二组连续元素。 该指令不能将不连续的元素组从输入向量路由到指令的合成向量。 还描述了使用该指令的软件流水线

公开(公告)号：US20180088945A1

公开(公告)日：2018-03-29

申请号：US15274849

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  IGOR ERMOLAEV

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30021

Abstract: Systems, methods, and apparatuses relating to multiple source blend operations are described. In one embodiment, a processor is to execute an instruction to: receive a first input operand of a first input vector, a second input operand of a second input vector, and a third input operand of a third input vector, compare each element from the first input vector to each corresponding element of the second input vector to produce a first comparison vector, compare each element from the first input vector to each corresponding element of the third input vector to produce a second comparison vector, compare each element from the second input vector to each corresponding element of the third input vector to produce a third comparison vector, determine a middle value for each element position of the input vectors from the comparison vectors, and output the middle values into same element positions in an output vector.

公开(公告)号：US20170329609A1

公开(公告)日：2017-11-16

申请号：US15528079

申请日：2014-12-17

Applicant: INTEL CORPORATION

Inventor： DMITRY SIVKOV ,  IGOR ERMOLAEV

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30076 ,  G06F9/30145

Abstract: An apparatus and method for performing a spin-loop jump. One embodiment of a processor comprises: jump-pause execution logic to execute a jump-pause instruction, the jump-pause instruction to specify a condition and identify a destination instruction; wherein responsive to the execution of the jump-pause instruction, the jump-pause execution logic is to provide a hint that a loop between the jump-pause instruction and the destination instruction comprises a spin-wait loop and to test the condition, the jump-pause execution logic to delay execution by a specified amount prior to jumping to the destination instruction if the condition is satisfied. A second embodiment of a processor comprises test-subtract execution logic to execute a test-subtract instruction, the test-subtract instruction to decrement the counter value in a second source register, the test-subtract execution logic to further test the monitored value in a first source register or memory and the counter value in the second source register, wherein the test-subtract execution logic is to exit a spin-wait loop if the monitored value has a value indicating an exit condition or if the counter value is equal to zero.