公开(公告)号：US20170300334A1

公开(公告)日：2017-10-19

申请号：US15477374

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： DENIS M. KHARTIKOV ,  NAVEEN NEELAKANTAM ,  JOHN H. KELM ,  POLYCHRONIS XEKALAKIS

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

公开(公告)号：US20150277916A1

公开(公告)日：2015-10-01

申请号：US14228690

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： DENIS M. KHARTIKOV ,  NAVEEN NEELAKANTAM ,  JOHN H. KELM ,  POLYCHRONIS XEKALAKIS

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

Abstract translation: 用于优化的动态无序超长指令字（VLIW）管道的硬件/软件协同设计。 例如，一种装置的一个实施例包括：指令提取单元，用于从存储器以其程序顺序获取超长指令字（VLIW），每个VLIW包括分组到多个指令集计算（RISC）指令音节中的多个简化指令集计算（RISC）指令音节 VLIWs以一个顺序消除数据流依赖性和错误输出依赖关系之间的音节; 解码单元，以编程顺序对VLIW进行解码，并并行输出每个经解码的VLIW的音节; 以及优先与其他音节并行地执行音节的无序执行引擎，其中至少一些音节将以与从解码单元接收的顺序不同的顺序执行，出口 具有一个或多个处理阶段的执行引擎，当执行操作时，该处理阶段不检查数据流依赖性和音节之间的错误输出依赖性。