公开(公告)号：US09851976B2

公开(公告)日：2017-12-26

申请号：US14581101

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Wing Shek Wong ,  James E. Phillips

IPC: G06F9/38

CPC classification number: G06F9/3838

Abstract: A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.