公开(公告)号：US11074213B2

公开(公告)日：2021-07-27

申请号：US16457993

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Jay O'Neill ,  Jeroen Leijten ,  Harm Peters ,  Eugene Scuteri

IPC: G06F15/80 ,  G06F15/78

Abstract: Systems, methods, and apparatuses relating to vector processor architecture having an array of identical circuit blocks are described. In one embodiment, a processor includes a single centralized circuit comprising an instruction decoder and a controller; and a plurality of circuit slices that each comprise an arithmetic logic unit, a multiplier, a register file, a local memory, and a same plurality of logic circuits and a packed data datapath in between, wherein each circuit slice includes a physical port that provides a unique identification value that identifies a circuit slice from the other circuit slices, and the controller is to broadcast a same configuration value to the plurality of circuit slices to cause a first circuit slice to enable a first logic circuit and enable a second logic circuit of the first circuit slice based on its unique identification value and the configuration value, and cause a second circuit slice to enable a same, first logic circuit and disable a same, second logic circuit of the second circuit slice based on its unique identification value and the configuration value.