公开(公告)号：US20200083645A1

公开(公告)日：2020-03-12

申请号：US16468271

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Jeffrey LEE ,  Brent R. ROTHERMEL ,  Kemal AYGUN

IPC: H01R13/6471 ,  H01R13/6587 ,  H01R43/20

Abstract: Electrical connector technology is disclosed. In one example, a connector for coupling an electronics sub-assembly to an electronics assembly comprises a connector body having and a sub-assembly interface configured to electrically couple to an electronics sub-assembly. The connector has a circuit board interface configured to electrically couple to a circuit board of an electronics assembly. The connector has at least two rows of contacts configured to electrically couple the circuit board to the electronics sub-assembly. The at least two rows of contacts are aligned offset relative to each other such that any ground contact of one row avoids intersection of a plane in which any ground contact of the other row resides to at least partially cancel row-to-row crosstalk when the at least two rows of contacts are transmitting signals at a predetermined high-speed bit rate.

公开(公告)号：US20190394876A1

公开(公告)日：2019-12-26

申请号：US16559286

申请日：2019-09-03

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Tao WU ,  Gaurav CHAWLA ,  Jeffrey LEE

IPC: H05K1/11

Abstract: A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.