公开(公告)号：US20230197601A1

公开(公告)日：2023-06-22

申请号：US17558423

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jiun-Ruey Chen ,  Christopher Jezewski ,  John Plombon ,  Miriam Reshotko ,  Mauro Kobrinsky ,  Scott B. Clendenning

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5328 ,  H01L23/53238 ,  H01L21/76879 ,  H01L21/76807

Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.