公开(公告)号：US20220100514A1

公开(公告)日：2022-03-31

申请号：US17134367

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Anant NORI ,  Shankar BALACHANDRAN ,  Sreenivas SUBRAMONEY ,  Joydeep RAKSHIT ,  Vedvyas SHANBHOGUE ,  Avishaii ABUHATZERA ,  Belliappa KUTTANNA

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.