公开(公告)号：US20230168959A1

公开(公告)日：2023-06-01

申请号：US17538052

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Norma Bettine ,  Pavan Kumar ,  Justin Tippetts

IPC: G06F11/07 ,  G11C5/14

CPC classification number: G06F11/0754 ,  G06F11/0706 ,  G06F11/0772 ,  G11C5/148 ,  G06F9/4401

Abstract: Disclosed herein are systems and methods for self-isolation of power-management integrated circuits (PMICs) of memory modules under and in response to fault conditions. In an embodiment, a PMIC is operably engaged with a memory module that is operably engaged with a platform. The memory module includes a non-volatile-memory block having a power supply controlled by the PMIC. The PMIC has a critical-fault signal pin that can be asserted to shut down the platform. The PMIC determines whether at least one critical fault occurred during a prior cycle, and also determines whether a critical fault occurs during a bootup sequence during a current cycle. Based on determining that a prior-cycle critical fault occurred and that a critical fault occurs during the bootup sequence, the PMIC sets a critical-fault indicator corresponding to the current critical fault; powers down the power supply; and does not assert the critical-fault signal pin.