公开(公告)号：US20210349831A1

公开(公告)日：2021-11-11

申请号：US16911931

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ARAVINDH ANANTARAMAN ,  K. PATTABHIRAMAN ,  ANKUR SHAH

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/0837 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/123 ,  G06F9/30 ,  G06F9/50

Abstract: Described herein is an accelerator device having a cache memory for which limits may be specified for a memory allocation according to a class of service associated with a thread, application, or virtual machine that created the memory allocation. The limits can include a specific set of enumerated cache ways that are designated as eligible to cache data for memory allocations associated with a class of service.