公开(公告)号：US20220206800A1

公开(公告)日：2022-06-30

申请号：US17134136

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  JOONMOO HUH ,  KONSTANTINOS KROMMYDAS ,  MD FAIJUL AMIN

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

Abstract: Systems, methods, and apparatuses relating to one or more instructions for row or column aligning of a tile of a matrix operations accelerator are described. In one embodiment, a system includes a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to cause a third two-dimensional matrix to be logically formed for input into the two-dimensional grid of processing elements from the first two-dimensional matrix and the second two-dimensional matrix without moving data elements within the first plurality of registers and the second plurality of registers, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode.