公开(公告)号：US11216556B2

公开(公告)日：2022-01-04

申请号：US16222785

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Ken Grewal ,  Ravi Sahita ,  David Durham ,  Erdem Aktas ,  Sergej Deutsch ,  Abhishek Basak

IPC: G08B23/00 ,  G06F12/16 ,  G06F12/14 ,  G06F11/00 ,  G06F21/55 ,  G06F9/38 ,  G06F12/0891

Abstract: The present disclosure is directed to systems and methods that maintain consistency between a system architectural state and a microarchitectural state in the system cache circuitry to prevent a side-channel attack from accessing secret information. Speculative execution of one or more instructions by the processor circuitry causes memory management circuitry to transition the cache circuitry from a first microarchitectural state to a second microarchitectural state. The memory management circuitry maintains the cache circuitry in the second microarchitectural state in response to a successful completion and/or retirement of the speculatively executed instruction. The memory management circuitry reverts the cache circuitry from the second microarchitectural state to the first microarchitectural state in response to an unsuccessful completion, flushing, and/or retirement of the speculatively executed instruction.

公开(公告)号：US20190138720A1

公开(公告)日：2019-05-09

申请号：US16222785

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Ken Grewal ,  Ravi Sahita ,  David Durham ,  Erdem Aktas ,  Sergej Deutsch ,  Abhishek Basak

IPC: G06F21/55 ,  G06F9/38 ,  G06F12/0891 ,  G06F12/14

Abstract: The present disclosure is directed to systems and methods that maintain consistency between a system architectural state and a microarchitectural state in the system cache circuitry to prevent a side-channel attack from accessing secret information. Speculative execution of one or more instructions by the processor circuitry causes memory management circuitry to transition the cache circuitry from a first microarchitectural state to a second microarchitectural state. The memory management circuitry maintains the cache circuitry in the second microarchitectural state in response to a successful completion and/or retirement of the speculatively executed instruction. The memory management circuitry reverts the cache circuitry from the second microarchitectural state to the first microarchitectural state in response to an unsuccessful completion, flushing, and/or retirement of the speculatively executed instruction.