公开(公告)号：US20220214909A1

公开(公告)日：2022-07-07

申请号：US17703691

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Kunal Mehta

IPC: G06F9/455 ,  H04L9/08

Abstract: An apparatus provides a processor configured to execute instructions of a hypervisor to provide hypervisor-managed linear address translation (HLAT) with integrity protection. The processor is to execute the instructions to select a first key identifier for a first virtual machine to run on the hypervisor, invoke a first platform configuration instruction to configure the first key identifier in the processor including generating an encryption key for the first key identifier and setting an integrity mode for the first key identifier, instantiate the first virtual machine including a first guest kernel, the first guest kernel to allocate a plurality of HLAT paging structures to be used to translate a guest virtual address to a guest physical address of a first memory page allocated for the first virtual machine, mark the plurality of HLAT paging structures with read-only permission, and assign the first key identifier to the first memory page.

公开(公告)号：US12175247B2

公开(公告)日：2024-12-24

申请号：US17359306

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Balaji Masanamuthu Chinnathurai ,  Kunal Mehta ,  Brian L. Vajda

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses to support instructions for a hardware assisted heterogeneous instruction set architecture dispatcher are described. In one embodiment, a hardware processor includes a plurality of processor cores comprising a first type of processor core that supports a first instruction set architecture and a second type of processor core that supports a second different instruction set architecture, a decoder circuit of a processor core of the plurality of processor cores to decode a single instruction into a decoded single instruction, the single instruction including a field that identifies a requested core type and an opcode that indicates an execution circuit of the processor core is to: read a register to determine a core type of the processor core, cause the processor core to enter a first mode, that only permits execution of the first instruction set architecture by the processor core, when the requested core type and the core type of the processor core are the first type, cause the processor core to enter a second mode, that only permits execution of the second different instruction set architecture by the processor core, when the requested core type and the core type of the processor core are the second type, cause the processor core to enter a third mode, that only permits execution of the first instruction set architecture by the processor core, when the requested core type is the second type and the core type of the processor core is the first type, and cause the processor core to enter a fourth mode, that only permits execution of the second different instruction set architecture by the processor core, when the requested core type is the first type and the core type of the processor core is the second type, and the execution circuit of the processor core to execute the decoded single instruction according to the opcode.