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1.发明申请公开(公告)号：US20210200673A1
公开(公告)日：2021-07-01
申请号：US16728800
申请日：2019-12-27
申请人： Intel Corporation
发明人： DEEPAK GUPTA , MINGWEI ZHANG , RAVI SAHITA , VEDVYAS SHANBHOGUE , MICHAEL LEMAY , DAVID M. DURHAM
IPC分类号： G06F12/02 , G06F12/0895 , G06F9/30
摘要： An apparatus and method for memory management using compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request using a first linear address; and address translation circuitry to perform a first walk operation through a set of one or more address translation tables to translate the first linear address to a first physical address, the address translation circuitry to concurrently perform a second walk operation through a set of one or more linear address metadata tables to identify metadata associated with the linear address, and to use one or more portions of the metadata to validate access by the at least one instruction to the first physical address.
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公开(公告)号：US20190102567A1
公开(公告)日：2019-04-04
申请号：US15721082
申请日：2017-09-29
申请人： Intel Corporation
摘要： Apparatuses for computing are disclosed herein. In embodiments, an apparatus may include one or more processors, a memory, and a compiler to be operated by the one or more processors to compile a computer program. The compiler may include one or more analyzers to parse and analyze source code of the computer program that generates pointers or de-references pointers. The compiler may also include a code generator coupled to the one or more analyzers to generate executable instructions for the source code of the computer program including insertion of additional encryption or decryption executable instructions into the computer program, based at least in part on a result of the analysis, to authenticate memory access operations of the source code.
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