公开(公告)号：US20210407618A1

公开(公告)日：2021-12-30

申请号：US16912498

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Aravinda Radhakrishnan ,  Marcus Wing-Kin Cheung ,  Dinesh Somasekhar ,  Naga Mallika Bhandaru ,  Michael Nelms ,  Rodrigo Gonzalez Gutierrez ,  Kaitlyn Chen

IPC: G11C29/00

Abstract: Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.