公开(公告)号：US12182025B2

公开(公告)日：2024-12-31

申请号：US18321603

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Neha Gholkar ,  Akhilesh Kumar

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/121

Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

公开(公告)号：US20240202125A1

公开(公告)日：2024-06-20

申请号：US18084054

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Neha Gholkar ,  Akhilesh Kumar

IPC: G06F12/084 ,  G06F12/0817 ,  G06F12/0891

CPC classification number: G06F12/084 ,  G06F12/082 ,  G06F12/0891

Abstract: An example of an apparatus may include memory, two or more caches, and circuitry coupled to the memory and the two or more caches to selectively maintain coherency of data shared among the memory and the two or more caches based on coherency bypass information associated with the data. Other examples are disclosed and claimed.

公开(公告)号：US11656997B2

公开(公告)日：2023-05-23

申请号：US16696548

申请日：2019-11-26

Applicant: Intel Corporation

Inventor： Neha Gholkar ,  Akhilesh Kumar

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/121

CPC classification number: G06F12/0891 ,  G06F12/121 ,  G06F2212/1044 ,  G06F2212/60

Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.