公开(公告)号：US20220222178A1

公开(公告)日：2022-07-14

申请号：US17710806

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Sai Prashanth MURALIDHARA ,  Wei P. CHEN ,  Nishant SINGH ,  Sharada VENKATESWARAN ,  Daniel W. LIU

IPC: G06F12/0811 ,  G06F12/0815

Abstract: A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.