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公开(公告)号:US12066939B2
公开(公告)日:2024-08-20
申请号:US17086243
申请日:2020-10-30
Applicant: Intel Corporation
Inventor: Rahul R. Shah , Omkar Maslekar , Priya Autee , Edwin Verplanke , Andrew J. Herdrich , Jeffrey D. Chamberlain
IPC: G06F12/00 , G06F9/30 , G06F12/0811 , G06F12/084 , G06F12/1009
CPC classification number: G06F12/0811 , G06F9/30047 , G06F9/30079 , G06F12/084 , G06F12/1009
Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.