公开(公告)号：US20250077232A1

公开(公告)日：2025-03-06

申请号：US18882364

申请日：2024-09-11

Applicant: Intel Corporation

Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

IPC: G06F9/38 ,  G06F13/28 ,  G06T1/20

Abstract: A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.

公开(公告)号：US20200218539A1

公开(公告)日：2020-07-09

申请号：US16243663

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

IPC: G06F9/38 ,  G06F13/28 ,  G06T1/20

Abstract: A graphics processing device comprises a set of compute units to execute multiple threads of a workload, a cache coupled with the set of compute units, and a prefetcher to prefetch instructions associated with the workload. The prefetcher is configured to use a thread dispatch command that is used to dispatch threads to execute a kernel to prefetch instructions, parameters, and/or constants that will be used during execution of the kernel. Prefetch operations for the kernel can then occur concurrently with thread dispatch operations.

公开(公告)号：US20220083339A1

公开(公告)日：2022-03-17

申请号：US17509726

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

IPC: G06F9/38 ,  G06T1/20 ,  G06F13/28

Abstract: A graphics processing device comprises a set of compute units to execute multiple threads of a workload, a cache coupled with the set of compute units, and a prefetcher to prefetch instructions associated with the workload. The prefetcher is configured to use a thread dispatch command that is used to dispatch threads to execute a kernel to prefetch instructions, parameters, and/or constants that will be used during execution of the kernel. Prefetch operations for the kernel can then occur concurrently with thread dispatch operations.

公开(公告)号：US20230401064A1

公开(公告)日：2023-12-14

申请号：US18347964

申请日：2023-07-06

Applicant: Intel Corporation

Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

IPC: G06F9/38 ,  G06T1/20 ,  G06F13/28

CPC classification number: G06F9/3802 ,  G06T1/20 ,  G06F13/28

Abstract: A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.