公开(公告)号：US20200285471A1

公开(公告)日：2020-09-10

申请号：US16881920

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： PRATIK J. ASHAR ,  SUPRATIM PAL ,  SUBRAMANIAM MAIYURAN ,  WEI-YU CHEN ,  GUEI-YUAN LUEH

IPC: G06F9/30 ,  G06F9/50 ,  G06F8/41

Abstract: An apparatus to facilitate register sharing is disclosed. The apparatus includes one or more processors to generate first machine code having a first General Purpose Register (GRF) per thread ratio, detect an occurrence of one or more spill/fill instructions in the first machine code, and generate second machine code having a second GRF per thread ratio upon a detection of one or more spill/fill instructions in the first machine code, wherein the second GRF per thread ratio is based on a disabling of a first of a plurality of hardware threads

公开(公告)号：US20200073664A1

公开(公告)日：2020-03-05

申请号：US16120226

申请日：2018-09-01

Applicant: Intel Corporation

Inventor： PRATIK J. ASHAR ,  SUPRATIM PAL ,  SUBRAMANIAM MAIYURAN ,  WEI-YU CHEN ,  GUEI-YUAN LUEH

IPC: G06F9/30 ,  G06F9/50

Abstract: An apparatus to facilitate register sharing is disclosed. The apparatus includes one or more processors to generate first machine code having a first General Purpose Register (GRF) per thread ratio, detect an occurrence of one or more spill/fill instructions in the first machine code, and generate second machine code having a second GRF per thread ratio upon a detection of one or more spill/fill instructions in the first machine code, wherein the second GRF per thread ratio is based on a disabling of a first of a plurality of hardware threads