公开(公告)号：US20180285119A1

公开(公告)日：2018-10-04

申请号：US15562408

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Alexandr Titov ,  Dmitry Maslennikov ,  Sergey Y. SHISHLOV ,  Valentin Burov ,  Pavel Matveyev

IPC: G06F9/38

Abstract: A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.