公开(公告)号：US20190042544A1

公开(公告)日：2019-02-07

申请号：US16122030

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Sidharth N. KASHYAP ,  Angus LEPPER ,  Peter BOYLE

IPC: G06F17/16 ,  G06F7/544 ,  G06N5/04 ,  G06F9/30 ,  G06N3/08

Abstract: Disclosed embodiments relate to mixed-precision vector multiply-accumulate (MPVMAC) In one example, a processor includes fetch circuitry to fetch a compress instruction having fields to specify locations of a source vector having N single-precision formatted elements, and a compressed vector having N neural half-precision (NHP) formatted elements, decode circuitry to decode the fetched compress instruction, execution circuitry to respond to the decoded compress instruction by: converting each element of the source vector into the NHP format and writing each converted element to a corresponding compressed vector element, wherein the processor is further to fetch, decode, and execute a MPVMAC instruction to multiply corresponding NHP-formatted elements using a 16-bit multiplier, and accumulate each of the products with previous contents of a corresponding destination using a 32-bit accumulator.