公开(公告)号：US20190303159A1

公开(公告)日：2019-10-03

申请号：US15940768

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Joshua B. FRYMAN ,  Jason M. HOWARD ,  Priyanka SURESH ,  Banu Meenakshi NAGASUNDARAM ,  Srikanth DAKSHINAMOORTHY ,  Ankit MORE ,  Robert PAWLOWSKI ,  Samkit JAIN ,  Pranav YEOLEKAR ,  Avinash M. SEEGEHALLI ,  Surhud KHARE ,  Dinesh SOMASEKHAR ,  David S. DUNNING ,  Romain E. Cledat ,  William Paul GRIFFIN ,  Bhavitavya B. BHADVIYA ,  Ivan B. GANEV

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).