公开(公告)号：US20230112575A1

公开(公告)日：2023-04-13

申请号：US18080980

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Prerna Budhkar ,  Tanvi Sharma ,  Srivatsa Rangachar Srinivasa ,  Dileep John Kurian ,  Tanay Karnik

IPC: G06F12/0864 ,  G06F12/14

Abstract: A hash accelerator of a cache memory may receive a query from a processor comprising the cache memory, the query to comprise an input key and an operation to be performed based on a hash table stored in the cache memory. The hash accelerator may determine whether an entry associated with the input key exists in a lock board of the hash accelerator. The hash accelerator may process the query based on whether the entry exists in the lock board.

公开(公告)号：US20240320490A1

公开(公告)日：2024-09-26

申请号：US18734487

申请日：2024-06-05

Applicant: Intel Corporation

Inventor： Jainaveen Sundaram Priya ,  Prerna Budhkar ,  Vui Seng Chua ,  Srivatsa Rangachar Srinivasa ,  Tanay Karnik

IPC: G06N3/08 ,  G06N3/048

CPC classification number: G06N3/08 ,  G06N3/048

Abstract: A modified 2-pass version of the SoftMax operation can be implemented to address reduce computational cost without loss of accuracy, in particular for deep learning neural networks such as transformer-based neural networks and large language models (LLMs). The first pass is modified to include two scalar operations at the end. At the end of the first pass, a first scalar operation is performed to calculate a logarithm of the denominator, and a second scalar operation is performed to calculate an operand value based on a sum of the logarithm of the denominator and the maximum value. The second pass is modified to perform addition and exponentiation. In the second pass, an element of an input tensor is subtracted by the operand value to obtain an exponent, and a base is raised to the exponent. The second pass avoids divisions.