公开(公告)号：US10932202B2

公开(公告)日：2021-02-23

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/861 ,  H04W28/00 ,  H04W52/24 ,  H04W24/10 ,  H04B17/336 ,  H04W72/04 ,  H04L1/00 ,  H04L12/883 ,  H04W52/36 ,  H04W52/42 ,  H04B7/0413

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

公开(公告)号：US20190294570A1

公开(公告)日：2019-09-26

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/883

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.