公开(公告)号：US20230401130A1

公开(公告)日：2023-12-14

申请号：US17840211

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Rakesh Mehta ,  Hanmanthrao Patli ,  Ivan Herrera Mejia ,  Raj Chandar Rasappan ,  Hagay Spector ,  Renu Patle ,  Fylur Rahman Sathakathulla ,  Ruchira Liyanage ,  Raju Kasturi ,  Fred Steinberg ,  Ananth Gopalakrishnan ,  Satish Venkatesan ,  Pradyumna Reddy Patnam ,  Suresh Pothukuchi ,  Tapan Ganpule ,  Atthar H. Mohammed ,  Altug Koker

IPC: G06F11/22 ,  G06F11/07

CPC classification number: G06F11/2236 ,  G06F11/0721 ,  G06F11/079

Abstract: One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package. The graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device and excludes functionality that is implemented in a separate due of the multi-die SoC. The apparatus includes a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality provided by the separate die of the multi-die SoC device, which enables silicon validation of the graphics processor die separately from other dies of the multi-die SoC.