公开(公告)号：US20240421150A1

公开(公告)日：2024-12-19

申请号：US18209358

申请日：2023-06-13

Applicant: Intel Corporation

Inventor： Ritesh Agarwal ,  Harshit Dhakad ,  Krzysztof Domanski

IPC: H01L27/02

Abstract: Techniques and mechanisms for selectively disabling functionality of a power clamp circuit which is to mitigate damage due to electrostatic discharge (ESD). In an embodiment, a shut-off circuit is coupled to receive a control signal which indicates an actual or expected future power state transition of a load. The power clamp circuit comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. Based on a filtered version of the control signal, the shut-off circuit generates a first one or more signals to selectively disable the pull-up circuit. The shut-off circuit further generates a second one or more signals, based on the filtered version of the control signal, to selectively disable the pull-down circuit.