公开(公告)号：US20240005135A1

公开(公告)日：2024-01-04

申请号：US18135958

申请日：2023-04-18

Applicant: Intel Corporation

Inventor： Avishaii Abuhatzera ,  Om Ji Omer ,  Ritwika Chowdhury ,  Lance Hacking

IPC: G06N3/063 ,  G06N3/088 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/045 ,  G06N3/088

Abstract: An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.

公开(公告)号：US20200320375A1

公开(公告)日：2020-10-08

申请号：US16909295

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Avishaii Abuhatzera ,  Om Ji Omer ,  Ritwika Chowdhury ,  Lance Hacking

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.

公开(公告)号：US11714998B2

公开(公告)日：2023-08-01

申请号：US16909295

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Avishaii Abuhatzera ,  Om Ji Omer ,  Ritwika Chowdhury ,  Lance Hacking

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06N3/088

CPC classification number: G06N3/063 ,  G06N3/0454 ,  G06N3/088

Abstract: An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.