公开(公告)号：US11095560B2

公开(公告)日：2021-08-17

申请号：US15859390

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Gary Muntz ,  Robert Zak ,  Thomas Lovett ,  Michael A. Parker

IPC: H04L12/803 ,  H04L12/66 ,  H04L12/801 ,  H04L12/851 ,  H04L12/825

Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.

公开(公告)号：US11645534B2

公开(公告)日：2023-05-09

申请号：US16127416

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sayantan Sur ,  James Dinan ,  Maria Garzaran ,  Anupama Kurpad ,  Andrew Friedley ,  Nusrat Islam ,  Robert Zak

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N3/084

CPC classification number: G06N3/084 ,  G06N3/04 ,  G06N3/063

Abstract: An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.

公开(公告)号：US20190044864A1

公开(公告)日：2019-02-07

申请号：US15859390

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Gary Muntz ,  Robert Zak ,  Thomas Lovett ,  Michael A. Parker

IPC: H04L12/803 ,  H04L12/66 ,  H04L12/801 ,  H04L12/851 ,  H04L12/825

Abstract: Technologies for Ethernet gateway congestion management in HPC architectures include a high-performance computing (HPC) switch with an Ethernet gateway that is configured to receive an HPC packet from an HPC fabric via a virtual lane (VL) of the Ethernet gateway. The Ethernet gateway is further configured to determine whether the HPC packet corresponds to a backward error correction notification (BECN), identify one or more priority code points (PCPs) of the HPC packet corresponding to a BECN as a function of the VL on which the HPC packet was received, and generate an Ethernet priority-based flow control (PFC) frame that includes the one or more identified PCPs in a header of the Ethernet PFC frame. Additionally, the Ethernet gateway is configured to transmit the Ethernet PFC frame to an Ethernet fabric as a function of the one or more identified PCPs. Other embodiments are described herein.

公开(公告)号：US20190042946A1

公开(公告)日：2019-02-07

申请号：US16127416

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sayantan Sur ,  James Dinan ,  Maria Garzaran ,  Anupama Kurpad ,  Andrew Friedley ,  Nusrat Islam ,  Robert Zak

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.