公开(公告)号：US20160179523A1

公开(公告)日：2016-06-23

申请号：US14582171

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Elmoustapha OULD-AHMED-VALL ,  David GUILLEN FANDOS ,  Jesus F. SANCHEZ ,  Guillem SOLE ,  Roger ESPASA

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30018 ,  G06F9/30036

Abstract: An apparatus and method are described for performing a vector broadcast and XORAND logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory indicating a destination packed data operand, a first source packed data operand, a second source packed data operand, and an immediate operand, and execution logic to determine a bit in the second source packed data operand based a position corresponding to the immediate value, perform a bitwise AND between the first source packed data operand and the determined bit to generate an intermediate result, perform a bitwise XOR between the destination packed data operand and the intermediate result to generate a final result, and store the final result in a storage location indicated by the destination packed data operand.

Abstract translation: 描述了用于执行向量广播和XORAND逻辑指令的装置和方法。 例如，处理器的一个实施例包括：提取逻辑，用于从存储器取出指令，指示目的地打包数据操作数，第一源打包数据操作数，第二源打包数据操作数和立即操作数，以及执行逻辑，以确定 在第二源打包数据操作数中基于对应于立即数的位置的位，在第一源打包数据操作数和确定的位之间执行按位AND，以产生中间结果，在目的地打包数据操作数与 中间结果以产生最终结果，并将最终结果存储在由目的地打包数据操作数指示的存储位置中。

公开(公告)号：US20190138303A1

公开(公告)日：2019-05-09

申请号：US16110298

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Elmoustapha OULD-AHMED-VALL ,  David GUILLEN FANDOS ,  Jesus F. SANCHEZ ,  Guillem SOLE ,  Roger ESPASA

IPC: G06F9/30 ,  G06F9/34

Abstract: An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.

公开(公告)号：US20160283242A1

公开(公告)日：2016-09-29

申请号：US14582170

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Elmoustapha OULD-AHMED-VALL ,  David GUILLEN FANDOS ,  Jesus F. SANCHEZ ,  Guillem SOLE ,  Roger ESPASA

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/34

Abstract: An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.

Abstract translation: 描述了用于执行向量水平逻辑指令的装置和方法。 例如，处理器的一个实施例包括：从存储器取出指令的提取逻辑，以及执行逻辑，用于从立即操作数的第一指定位组确定一个或多个数据元素的第一集合的值，其中位置 从所述立即数操作数的所述第一指定位组确定的所述第一组一个或多个数据元素是基于一个或多个索引值的第一集合，所述索引值具有与第一集合上的打包数据元素相对应的最高有效位 目的地打包数据操作数的一个或多个位置，并且具有对应于第一源打包数据操作数的对应位置处的数据元素的最低有效位。