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公开(公告)号：US20190044063A1
公开(公告)日：2019-02-07
申请号：US15942281
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Lorenzo Fratin , Russell L. Meyer , Fabio Pellizzer
IPC: H01L45/00
Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.
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