公开(公告)号：US20230129732A1

公开(公告)日：2023-04-27

申请号：US17464583

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： ALBERT SCHMITZ ,  ANNE MATSUURA ,  RAVI PILLARISETTY ,  SHAVINDRA PREMARATNE ,  JUSTIN HOGABOAM ,  LESTER LAMPERT

IPC: G06N10/70 ,  G06N10/20

Abstract: Apparatus and method for measurement-free (MF) quantum error correction (QEC). For example, one embodiment of a method comprises: determining an error syndrome on a first subset of ancilla qubits of a quantum processor; decoding the error syndrome to produce decoded results on a second subset of ancilla qubits of the quantum processor; applying the decoded results to one or more system qubits; and unconditionally resetting the first subset and/or second subset of ancilla qubits to remove entropy and/or noise from the quantum system, wherein the operations of determining the error syndrome, decoding the error syndrome, applying the error syndrome, and unconditionally resetting the first and/or second subset of ancilla qubits are performed responsive to a qubit controller executing quantum control instructions provided from or derived from a script and without transmitting measurement data related to the error syndrome to a non-quantum computing device.

公开(公告)号：US20230244459A1

公开(公告)日：2023-08-03

申请号：US17589647

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： XIANG ZOU ,  JUSTIN HOGABOAM ,  PRADNYA LAXMAN KHALATE ,  XIN-CHUAN WU ,  ANNE MATSUURA ,  SHAVINDRA PREMARATNE

IPC: G06F8/41

CPC classification number: G06F8/447

Abstract: Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of a method comprises: reading source code specifying both non-quantum operations to be performed by a host processor and quantum operations to be performed by a quantum accelerator; compiling the source code to generate a target object file, wherein portions of the source code specifying the quantum operations are compiled into quantum basic blocks (QBBs) in the target object file, each QBB comprising one or more quantum instructions to be executed by the quantum accelerator and wherein portions of the source code specifying the non-quantum operations are compiled into native instructions to be executed by the host processor.

公开(公告)号：US20210182725A1

公开(公告)日：2021-06-17

申请号：US16714663

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： XIANG ZOU ,  SHAVINDRA PREMARATNE

IPC: G06N10/00 ,  G06F9/30

Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

公开(公告)号：US20240346348A1

公开(公告)日：2024-10-17

申请号：US18091202

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： XIANG ZOU ,  SHAVINDRA PREMARATNE

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

公开(公告)号：US20210173660A1

公开(公告)日：2021-06-10

申请号：US16706550

申请日：2019-12-06

Applicant: Intel Corporation

Inventor： JUSTIN HOGABOAM ,  XIANG ZOU ,  SHAVINDRA PREMARATNE ,  NADER KHAMMASSI

IPC: G06F9/38 ,  G06N10/00

Abstract: Parallel streaming apparatus and method for parallel quantum computations. For example, one embodiment of a processor comprises: a memory interface coupled to a system memory; and a plurality of streaming multi-processors, each streaming multiprocessor to execute a plurality of instruction streams in parallel, the instruction streams including quantum instructions, each streaming multiprocessor comprising: an instruction cache to store a first plurality of the quantum instructions fetched from the memory; instruction issue circuitry to dispatch each quantum instruction of the first plurality for execution; a plurality of parallel quantum execution circuits, each parallel quantum execution circuit to execute a subset of the first plurality of quantum instructions, two or more of the first plurality of quantum instructions to be executed in parallel by a corresponding two or more of the parallel quantum execution circuits; and a plurality of wave generators to receive signals from the plurality of parallel quantum execution circuits responsive to execution of each of the first plurality of quantum instructions, the wave generators to responsively generate analog waveforms to control qubits of a quantum processor.