公开(公告)号：US20220197657A1

公开(公告)日：2022-06-23

申请号：US17130016

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： NIRANJAN KUMAR SOUNDARARAJAN ,  SREENIVAS SUBRAMONEY ,  SR SWAMY SARANAM CHONGALA

IPC: G06F9/38

Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.