公开(公告)号：US20240427679A1

公开(公告)日：2024-12-26

申请号：US18756550

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Renu Patle ,  Hanmanthrao Patli ,  Rakesh Mehta ,  Hagay Spector ,  Ivan Herrera Mejia ,  Fylur Rahman Sathakathulla ,  Gowtham Raj Karnam ,  Mohsin Ali ,  Sahar Sharabi ,  Abraham Halevi Fraenkel ,  Eyal Pniel ,  Ehud Cohn ,  Raghav Ramesh Lakshmi ,  Altug Koker

IPC: G06F11/26 ,  G06F9/30

Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

公开(公告)号：US20230401132A1

公开(公告)日：2023-12-14

申请号：US17840239

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Renu Patle ,  Hanmanthrao Patli ,  Rakesh Mehta ,  Hagay Spector ,  Ivan Herrera Mejia ,  Fylur Rahman Sathakathulla ,  Gowtham Raj Karnam ,  Mohsin Ali ,  Sahar Sharabi ,  Abraham Halevi Fraenkel ,  Eyal Pniel ,  Ehud Cohn ,  Raghav Ramesh Lakshmi ,  Altug Koker

IPC: G06F11/26 ,  G06F9/30

CPC classification number: G06F11/26 ,  G06F9/30072

Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

公开(公告)号：US12038819B2

公开(公告)日：2024-07-16

申请号：US17840239

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Renu Patle ,  Hanmanthrao Patli ,  Rakesh Mehta ,  Hagay Spector ,  Ivan Herrera Mejia ,  Fylur Rahman Sathakathulla ,  Gowtham Raj Karnam ,  Mohsin Ali ,  Sahar Sharabi ,  Abraham Halevi Fraenkel ,  Eyal Pniel ,  Ehud Cohn ,  Raghav Ramesh Lakshmi ,  Altug Koker

IPC: G06F11/26 ,  G06F9/30

CPC classification number: G06F11/26 ,  G06F9/30072

Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.