公开(公告)号：US20210374554A1

公开(公告)日：2021-12-02

申请号：US17402114

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Chandrakant Khandelwal ,  Ritesh Kumar Rajore ,  Laxmi Ganesan ,  Sai Jayanthi ,  Yamini Nimmagadda

IPC: G06N3/10 ,  G06F8/41 ,  G06F16/901

Abstract: Systems, apparatuses and methods may provide for technology that parses, at runtime, a deep learning graph in topological order to identify a plurality of nodes, marks a first set of nodes in the plurality of nodes as unsupported by target hardware, and marks a second set of nodes in the plurality of nodes as supported by the target hardware, wherein the first set of nodes and the second set of nodes are marked based on one or more attributes defining operation functionality, and wherein the one or more attributes include one or more of an input node parameter, a dimension, or a shape.

公开(公告)号：US12242973B2

公开(公告)日：2025-03-04

申请号：US17402114

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Chandrakant Khandelwal ,  Ritesh Kumar Rajore ,  Laxmi Ganesan ,  Sai Jayanthi ,  Yamini Nimmagadda

IPC: G06N3/10 ,  G06F8/41 ,  G06F9/445 ,  G06F16/901

Abstract: Systems, apparatuses and methods may provide for technology that parses, at runtime, a deep learning graph in topological order to identify a plurality of nodes, marks a first set of nodes in the plurality of nodes as unsupported by target hardware, and marks a second set of nodes in the plurality of nodes as supported by the target hardware, wherein the first set of nodes and the second set of nodes are marked based on one or more attributes defining operation functionality, and wherein the one or more attributes include one or more of an input node parameter, a dimension, or a shape.