公开(公告)号：US12218840B2

公开(公告)日：2025-02-04

申请号：US16902371

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Elazar Cohen ,  Shaul Yifrach ,  Parthasarathy Sarangam

IPC: H04L45/7453 ,  H04L45/00 ,  H04L45/745 ,  H04L69/22

Abstract: Flexible schemes for adding rules to a NIC pipeline and associated apparatus. Multiple match-action tables are implemented in host memory of a platform defining actions to be taken for matching packet flows. A packet processing pipeline and an exact match (EM) cache is implemented on a network interface, such as a NIC, installed in the platform. A portion of the match-action entries in the host memory match-action tables are cached in the EM cache. Received packets are processed to generate a key that is used as a lookup for the EM cache. If a match is found, the action is taken. For a miss, the key is forwarded to the host software and the match-action tables are searched. For a match, the action is taken, and the entry is added to the EM cache. If no match is found, a new match-action entry is added to a match-action table. Aging-out mechanisms are used for the match-action tables and the EM cache. A multi-hash scheme is used to that supports a very large number of match-action entries.