公开(公告)号：US20190036683A1

公开(公告)日：2019-01-31

申请号：US16147649

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/60

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

公开(公告)号：US20190109703A1

公开(公告)日：2019-04-11

申请号：US16147644

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/60

CPC classification number: H04L9/0637 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30156 ,  G06F21/602 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/24 ,  H04L2209/80

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

公开(公告)号：US20180375642A1

公开(公告)日：2018-12-27

申请号：US16025706

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/60

CPC classification number: H04L9/0637 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30156 ,  G06F21/602 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/24 ,  H04L2209/80

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

公开(公告)号：US20250088348A1

公开(公告)日：2025-03-13

申请号：US18889148

申请日：2024-09-18

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F21/72 ,  G09C1/00

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

公开(公告)号：US20220006612A1

公开(公告)日：2022-01-06

申请号：US17480117

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G09C1/00 ,  G06F21/72

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

公开(公告)号：US20190109705A1

公开(公告)日：2019-04-11

申请号：US16147650

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/60

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

公开(公告)号：US20180359083A1

公开(公告)日：2018-12-13

申请号：US15973015

申请日：2018-05-07

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G09C1/00

CPC classification number: G06F21/72 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3895 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/125

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

公开(公告)号：US20210058236A1

公开(公告)日：2021-02-25

申请号：US17092133

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G09C1/00 ,  G06F21/72

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

公开(公告)号：US20200344045A1

公开(公告)日：2020-10-29

申请号：US16847626

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F9/38 ,  G09C1/00 ,  G06F21/72

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

公开(公告)号：US20190109704A1

公开(公告)日：2019-04-11

申请号：US16147646

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Shay GUERON ,  Vlad KRASNOV

IPC: H04L9/06 ,  G06F9/30 ,  G06F21/60

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.