公开(公告)号：US20190197019A1

公开(公告)日：2019-06-27

申请号：US15853303

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Saurabh Patil ,  Srajudheen Makkadayil ,  Rekha Manjunath ,  Tarjinder Singh ,  Vikram Sharma Mailthody

IPC: G06F15/80 ,  G06F17/16

CPC classification number: G06F15/8046 ,  G06F17/16

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

公开(公告)号：US20240168841A1

公开(公告)日：2024-05-23

申请号：US17993675

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Srajudheen Makkadayil ,  Jaijith K Radhakrishnan

IPC: G06F11/07 ,  G06F17/16

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F17/16

Abstract: An example of an apparatus may include matrix operation hardware and circuitry coupled to the matrix operation hardware to detect a hardware fault in the matrix operation hardware based at least in part on one or more hardware checksums of data in one or more matrices of the matrix operation hardware. Other embodiments are disclosed and claimed.

公开(公告)号：US20210319022A1

公开(公告)日：2021-10-14

申请号：US17358495

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Srajudheen Makkadayil ,  Somnath Paul ,  Shabbir Saifee ,  Bakshree Mishra ,  Vidhya Thyagarajan ,  Manoj Velayudha ,  Muhammad Khellah ,  Aniekeme Udofia

IPC: G06F16/2453 ,  G06F16/22

Abstract: Systems, apparatuses and methods include technology that determines, with a first processing engine of a plurality of processing engines, a first partial similarity measurement based on a first portion of a query vector and a first portion of a first candidate vector. The technology determines, with a second processing engine of the plurality of processing engines, a total similarity measurement based on the query vector and a second candidate vector. The technology determines, with the first processing engine, whether to compare a second portion of the query vector to a second portion of the first candidate vector based on the first partial similarity measurement and the total similarity measurement.

公开(公告)号：US11003620B2

公开(公告)日：2021-05-11

申请号：US15853303

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Saurabh Patil ,  Srajudheen Makkadayil ,  Rekha Manjunath ,  Tarjinder Singh ,  Vikram Sharma Mailthody

IPC: G06F15/80 ,  G06F17/16 ,  G06F17/11

Abstract: An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.