公开(公告)号：US10649746B2

公开(公告)日：2020-05-12

申请号：US15237443

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Abhay S. Kanhere ,  Paul Caprioli ,  Koichi Yamada ,  Suriya Madras-Subramanian ,  Srinivas Suresh

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F8/40 ,  G06F8/51 ,  G06F8/41

Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.