公开(公告)号：US20200004541A1

公开(公告)日：2020-01-02

申请号：US16021974

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Karthik SANKARANARAYANAN ,  Stephen J. TARSA ,  Gautham N. CHINYA ,  Helia NAEIMI

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.