公开(公告)号：US20220214973A1

公开(公告)日：2022-07-07

申请号：US17707010

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bruce RICHARDSON ,  Niall D. MCDONNELL ,  Subhiksha RAVISUNDAR

IPC: G06F12/0891 ,  G06F12/0842 ,  G06F12/0808 ,  G06F9/38

Abstract: Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU).