公开(公告)号：US20180189675A1

公开(公告)日：2018-07-05

申请号：US15396515

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Eriko NURVITADHI ,  Ganesh VENKATESH ,  Srivatsan KRISHNAN ,  Suchit SUBHASCHANDRA ,  Deborah MARR

IPC: G06N99/00 ,  G06F17/30

CPC classification number: G06N20/00 ,  G06F16/2237 ,  G06F16/285 ,  G06F17/16

Abstract: Hardware accelerator architectures for clustering are described. A hardware accelerator includes sparse tiles and very/hyper sparse tiles. The sparse tile(s) execute operations for a clustering task involving a matrix. Each sparse tile includes a first plurality of processing units to operate upon a first plurality of blocks of the matrix that have been streamed to one or more random access memories of the sparse tiles over a high bandwidth interface from a first memory unit. Each of the very/hyper sparse tiles are to execute operations for the clustering task involving the matrix. Each of the very/hyper sparse tiles includes a second plurality of processing units to operate upon a second plurality of blocks of the matrix that have been randomly accessed over a low-latency interface from a second memory unit.