公开(公告)号：US20160378446A1

公开(公告)日：2016-12-29

申请号：US14752440

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： TUGRUL INCE ,  KOICHI YAMADA

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/52 ,  G06F8/33 ,  G06F9/45516 ,  G06F21/79 ,  G06F2221/2141

Abstract: The present disclosure is directed to a system for binary translation version protection. Activity occurring in a device that may potentially cause native code to be altered may cause the device to prevent binary translations corresponding to the native code from being executed until a determination is made as to whether the binary translation needs to be regenerated. The native code may be stored in a memory page having an access permission that does not permit writes. Attempts to alter the native code would require the access permission of the memory page to be set to writable, which may cause a binary translation (BT) module to be notified of the potential change. The BT module may mark any binary translations corresponding to the native code as stale, and may cause a page permission control module to update memory pages including the binary translations to have an access permission of non-executable.

Abstract translation: 本公开涉及用于二进制翻译版本保护的系统。 在可能导致本地代码被改变的设备中发生的活动可能导致设备阻止对本地代码的二进制转换被执行，直到确定是否需要重新生成二进制翻译。 本地代码可以存储在具有不允许写入的访问权限的存储器页面中。 尝试更改本地代码将需要将内存页面的访问权限设置为可写入，这可能会导致二进制转换（BT）模块被通知潜在的更改。 BT模块可以将对应于本地代码的任何二进制转换标记为陈旧，并且可能导致页面许可控制模块更新包括二进制转换的存储器页面以具有不可执行的访问许可。

公开(公告)号：US20170371634A1

公开(公告)日：2017-12-28

申请号：US15194262

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： TUGRUL INCE ,  KOICHI YAMADA

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/52 ,  G06F9/45516

Abstract: The present disclosure is directed to a system for on-demand binary translation state map generation. Instead of interpreting the native code to be executed, binary translation circuitry (BT circuitry) may execute a binary translation (BT) in place of the native code. When a stop occurs (e.g., due to an interrupt, a modification of the native code, etc.), the BT circuitry may generate a binary translation state map (BT state map) that allows the location of the stop to be mapped back to the native code. Generation of the BT state map may involve determining a location and offset for the stop, performing region formation based on the location, loading instructions from the region (e.g., while accounting for the need to emulate instructions), forming the BT state map based at least on the size of the loaded instructions, and then mapping the stop back to the native code utilizing the offset.