公开(公告)号：US11126438B2

公开(公告)日：2021-09-21

申请号：US16452955

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Thomas Mullins ,  Ammon Christiansen ,  James Hadley ,  Robert S. Chappell ,  Sean Mirkes

IPC: G06F9/22 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a reservation station of a processor includes: a plurality of first lanes having a plurality of entries to store information for instructions having in-order dependencies; a variable latency tracking table including a second plurality of entries to store information for instructions having a variable latency; and a scheduler circuit to access a head entry of the plurality of first lanes to schedule, for execution on at least one execution unit, at least one instruction from the head entry of at least one of the plurality of first lanes. Other embodiments are described and claimed.