公开(公告)号：US20210082826A1

公开(公告)日：2021-03-18

申请号：US17102726

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Vipul Vijay MEHTA ,  Eric Jin LI ,  Sanka GANESAN ,  Debendra MALLIK ,  Robert Leon SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20190279938A1

公开(公告)日：2019-09-12

申请号：US16461316

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vipul Vijay MEHTA ,  Eric Jin LI ,  Sanka GANESAN ,  Debendra MALLIK ,  Robert Leon SANKMAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.