公开(公告)号：US11539660B2

公开(公告)日：2022-12-27

申请号：US17222962

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Vladimir Medvedkin ,  Andrey Chilikin

IPC: H04L61/2517 ,  H04L61/256 ,  H04L61/50

Abstract: Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.