公开(公告)号：US10802979B2

公开(公告)日：2020-10-13

申请号：US16473588

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Shu Xu ,  Tianyou Li ,  Zidong Jiang ,  Weiliang Lion Lin ,  Jinkui Ren ,  Chaobo Zhu ,  Xiaokang Qin

IPC: G06F12/10 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/0804 ,  G06F17/11

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

公开(公告)号：US10026143B2

公开(公告)日：2018-07-17

申请号：US15041795

申请日：2016-02-11

Applicant: Intel Corporation

Inventor： Kangyuan Shu ,  Junyong Ding ,  Yongnian Le ,  Weiliang Lion Lin ,  Xuefeng Deng ,  Yaojie Yan

IPC: G06T1/20 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

公开(公告)号：US20160335736A1

公开(公告)日：2016-11-17

申请号：US15041795

申请日：2016-02-11

Applicant: Intel Corporation

Inventor： Kangyuan Shu ,  Junyong Ding ,  Yongnian Le ,  Weiliang Lion Lin ,  Xuefeng Deng ,  Yaojie Yan

IPC: G06T1/20 ,  G06F9/50 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/5011 ,  G06F9/5044 ,  G06T1/60

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

公开(公告)号：US10726515B2

公开(公告)日：2020-07-28

申请号：US16025070

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： Kangyuan Shu ,  Junyong Ding ,  Yongnian Le ,  Weiliang Lion Lin ,  Xuefeng Deng ,  Yaojie Yan

IPC: G06T1/20 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

公开(公告)号：US20190332545A1

公开(公告)日：2019-10-31

申请号：US16473588

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Shu Xu ,  Tianyou Li ,  Zidong Jiang ,  Weiliang Lion Lin ,  Jinkui Ren ,  Chaobo Zhu ,  Xiaokang Qin

IPC: G06F12/0891 ,  G06F12/0804 ,  G06F12/06 ,  G06F17/11

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

公开(公告)号：US20190172174A1

公开(公告)日：2019-06-06

申请号：US16025070

申请日：2018-07-02

Applicant: Intel Corporation

Inventor： Kangyuan Shu ,  Junyong Ding ,  Yongnian Le ,  Weiliang Lion Lin ,  Xuefeng Deng ,  Yaojie Yan

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/50

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.