公开(公告)号：US20180004947A1

公开(公告)日：2018-01-04

申请号：US15201444

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： XIAONING LI ,  RAVI L. SAHITA ,  VEDVYAS SHANBHOGUE

IPC: G06F21/56 ,  G06F21/52

CPC classification number: G06F21/566 ,  G06F21/52 ,  G06F2221/033

Abstract: One embodiment provides a system. The system includes a processor comprising at least one processing unit; a memory; and control transfer (CT) logic. The CT logic is to determine whether a next instruction is a control transfer termination (CTT) when a prior instruction is a control transfer instruction (CTI). The CT logic is to determine whether the CTT is an external CTT, if the next instruction is the CTT; determine whether the prior instruction is an external CTI, if the CTT is the external CTT; and notify an external CTT fault, if the prior instruction is not the external CTI.